Accuracy-Aware Parametrizable TPU
Designed parametrizable MAC arithmetic datapaths supporting INT8, INT4, and INT2 inference. Performed RTL synthesis and preliminary ASIC physical implementation targeting GF180MCU.
#SystemVerilog#Yosys#OpenROAD
RESUME / CURRICULUM VITAE
Kanwar Pannu
Digital Design Engineer
Computer Engineering graduate specializing in digital design, computer architecture, and hardware acceleration for AI. Experienced across RTL development, verification, synthesis, FPGA implementation, and preliminary ASIC physical design.
Download Resume ↓01
Experience
2023 — 2025
Neuromorphics Researcher
York University
Designed and implemented spiking neural network algorithms in Python and PyTorch, exploring biologically inspired learning approaches for low-power AI hardware.
Collaborated with multidisciplinary researchers to translate neuroscience research into engineering documentation and designs.
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Education
2021 — 2026
Bachelor of Engineering — Computer Engineering
York University
Toronto, Canada
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Technical Skills
Hardware Design & EDA
VerilogSystemVerilogVerilatorModelSimYosysQuartusLibreLaneOpenROADLTspiceIcarus Verilog
Programming
PythonCC++NumPyPandasScikit-learncocotb
Development Tools
GitLinuxDockerMakeBashJupyter
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Selected Engineering Projects
ZeroCost-LLC
Developed a parametrizable set-associative last-level cache with LRU replacement, write-back and write-allocate policies, exploring predictable memory access for embedded systems.
#SystemVerilog#CacheArchitecture#RTL
5-Stage Pipelined RISC-V CPU
Designed a 32-bit in-order RISC-V processor with IF, ID, EX, MEM, and WB stages, including hazard detection, forwarding, stalls, and branch control.
#RISC-V#SystemVerilog#ProcessorDesign
FPGA CNN Accelerator
Implemented a convolutional spiking neural network on the DE10-Lite FPGA, with UART communication, automated verification, and MNIST inference.
#Verilog#FPGA#Python
ECG Monitoring & AI Anomaly Detection
Designed a MOSFET-based ECG analog front-end and integrated real-time signal acquisition with a Python ML pipeline and monitoring dashboard.
#LTspice#Arduino#Python
Tree Motion Energy Harvesting & IoT
Developed ESP32 firmware and a real-time monitoring pipeline for harvested energy and environmental sensor data.
#ESP32#EmbeddedSystems#IoT
Interested in my work?
Explore my engineering projects or get in touch.