ZeroCost-LLC

Overview

ZeroCost-LLC is a SystemVerilog implementation of a shared last-level cache architecture inspired by academic research into high-performance and predictable memory systems.

Motivation

Shared last-level caches play an important role in multicore processors. Their architecture influences memory access latency, throughput, and predictability.

This project explores architectural techniques for shared cache design.

Architecture

Architecture diagram and detailed explanation coming soon.

RTL Implementation

Implementation details coming soon.

Verification

Verification methodology and results coming soon.

Results

Simulation and synthesis results coming soon.

Future Work

• Expand verification coverage.
• Develop a UVM-based verification environment.
• Investigate additional architectural and performance characteristics.